1. Field of the Invention
The present invention is related to an interrupt control circuit of a data processing unit, especially, to an interrupt control circuit which accepts or holds an external interrupt request signal (or an interrupt request signal from an unit external to the data processing unit).
In recent years, many data processing units usually improve their processing performance by utilizing special facilities such as a pipeline and various types of buffers including cache memories, for instruction and data. Data processing units having such facilities can demonstrate increased processing performance when an external interrupt, e.g., an input/output interrupt and timer interrupt, is not triggered. When an external interrupt is triggered, performance decreases because it may invalidate instructions and data being processed in those facilities.
Accordingly, an interrupt control circuit which allows a data processing unit to demonstrate an increased processing performance, even when an external interrupt is triggered, is in great demand.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating an interrupt control circuit as is known in the prior art.
External interrupt (e.g., input/output interrupt and timer interrupt) request signals IRQ, with respective priority levels (e.g., 1-15) assigned, are first set in a state control register 15. The outputs from the state control register 15 are ANDed with interrupt-mask information (mask bits), which are set by a program in a mask register 16, by an AND circuit 11. The mask bits, corresponding to the external interrupt requests, specify whether to enable the corresponding interrupt requests. The interrupt request signal whose corresponding mask bit is set to 1 is selected by the AND circuit 11 to output logical 1 to a priority circuit 12. When a plurality of interrupt request signals are selected by the AND circuit 11, the priority circuit 12 selects only one of the highest priority level to enable for interrupt.
The interrupt request signal IQL is input to an execution unit 3a. When fetching, or after having fetched, an instruction from a programmed instruction stream, the execution unit 3a checks to see if there is an interrupt request signal IQL enabled. If there is, the execution unit 3a accepts the interrupt request and performs an interrupt function; otherwise, it fetches an instruction and executes the instruction fetched.
According to the related art as described above, when an external interrupt request IRQ is input while a data processing unit (hereinafter called a CPU) 1p is executing an instruction stream, the external interrupt request IRQ is accepted or held, simply depending on the interrupt-mask information stored in the mask register 15. That is, when the above condition of the interrupt-mask information is satisfied for an interrupt request, the CPU 1p accepts the interrupt request and performs interrupt operation, even when the interrupt request is of lower priority, i.e., not so urgent to interrupt the program immediately at the instruction being executed when the interrupt request is input.
Eventually, instructions and data in a cache memory and also instructions in a pipeline, which are all provided to achieve a high-speed processing performance of CPU 1p, become invalid and have to be discarded.